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IEEE Test Technology Educational Program 2016 
(TTEP'16)

Saturday 9 April
2016

Foz do Iguaçu, Brazil

http://ttep.tttc-events.org/ttep/tutorials.html 

Registration is open!


LATS 2016 - CALL FOR TUTORIALS PARTICIPATION

Scope


The Test Technology Educational Program (TTEP’16) of the TTTC is offering 2 half-day tutorials during the Saturday after the 17th IEEE Latin-American Test Symposium (LATS, previously Latin-American Test Workshop - LATW). This year, the TTEP tutorials will touch the most important topics of the test scenario, problems and solutions taught by recognized experts of the field. 

You can get detailed information on the TTEP website: http://ttep.tttc-events.org/ttep/tutorials.html

Registration


Register for the 17th IEEE Latin-American Test Symposium (LATS, previously Latin-American Test Workshop - LATW) in the Registration Page  http://www.feng.pucrs.br/~sisc/LATS2016/Registration.html

Program

April 9, 2016 (Saturday)

Morning (8:30 - 12:00)

Tutorial 1: 

Combining structural and functional test approaches across system levels

Authors:

  • Artur JUTMAN, Testonica Lab, ET
  • Hans-Joachim WUNDERLICH, University of Stuttgart, GR
  • Matteo SONZA REORDA, Politecnico di Torino, IT

This tutorial introduces into the best practices, current challenges and advanced techniques of high quality system-level test and diagnosis. Specialized techniques and industrial standards of testing complex systems (which may correspond to a System on Chip, board or interconnected system) are introduced. The reuse for system test of design for test structures and test data developed at module level is discussed, including the limitations and research challenges. Structural test methods have to be complemented by functional test methods; hence, state-of-the-art and leading edge research for functional testing are covered. Solutions change depending on the scenario (manufacturing test or in field test) and the goal (test or diagnosis). The tutorial also discusses the role of standards and regulations in the area. Test cases are described and discussed.

INTENDED AUDIENCE:
Board-level test, JTAG, Functional test, Structural test, Scan-based test,Embedded Instrumentation, Processor test
 

Afternoon (14:00 - 17:30)

Tutorial 2:

Hierarchical Test for Today’s SOC and IoT

Author:
  •  Yervant ZORIAN, SYNOPSYS, US
Today’s SoC and IoT design teams, use heterogeneous IP blocks from numerous sources, and multi-level hierarchical architecture (IPs, cores, subchips, chip). To test such SOCs and IoTs, DFT designers adopt new hierarchical test solutions across heterogeneous cores (memories, logic, AMS and interface IP), in order to support concurrent test, power reductions during test, DFT closure, isolated debug and diagnosis, pattern porting, calibration, and uniform access. This tutorial covers hierarchical test trends and solutions based on IEEE test standards, such as IEEE 1500, 1687 and 1149.1, along with intelligent infrastructure IP to help achieve the above advantages.

INTENDED AUDIENCE:

Engineers and managers responsible for design, test, quality or yield of a product; Engineers and managers responsible for product engineering and technology bring-up; Engineers involved in manufacturing production or process development; Anyone involved with the financial impact of low yield or low product quality.


Additional Information

Paolo Bernardi

TTEP Chair
Politecnico di Torino, I
Tel.: +39 011 564 7183
Fax: +39 011 564 7099
Email: paolo.bernardi@polito.it


Onnik Yaglioglu

TTEP Vice Chair (Program)
FormFactor Inc., USA
Email:  oyaglioglu@formfactor.com

Committee

GENERAL CHAIR

  • P. BERNARDI – Politecnico di Torino

VICE CHAIR (PROGRAM)

  • O. YAGLIOGLU  – FormFactor Inc., USA

PAST CHAIR

  • D. GIZOPOULOS – University of Athens

FINANCE CHAIR

  • C.-H. CHIANG – Alcatel-Lucent

PUBLICITY CHAIR

  • E. SANCHEZ – Politecnico di Torino

PLANNING CHAIR

  • Y. ZORIAN – Synopsis

INDUSTRIAL RELATIONS CHAIR

  • R. GALIVANCHE – INTEL Corporation

AUDIO/VISUAL CHAIRS

  • S. MENON – INTEL Corporation
  • O. SINANOGLU – NYU in Abu-Dhabi

ELECTRONIC MEDIA CHAIRS

  • S. DI CARLO – Politecnico di Torino
  • A. BOSIO – LIRMM 

ORGANIZING LIASONS

  • Y. ZORIAN - ITC'16
  • C. BOLCHINI - DATE'16
  • L. BOLZANI POEHLS - LATS'16
  • M. SONZA REORDA - VTS'16
  • Y. ZHANG - ATS'16
PROGRAM COMMITTEE
  • Robert C. Aitken – ARM, USA
  • Davide Appello – STMicroelectronics, I
  • Kanad Chakraborty – Lattice Semiconductor, USA
  • Sreejit Chakravarty – LSI logic, USA
  • Kun Young Chung – Samsung, USA
  • Scott Davidson – Oracle, USA
  • Anne E. Gattiker – IBM, USA
  • Kazumi Hatayama – NAIST, J
  • Doug Josephson – Intel Corporation, USA
  • Hans Manhaeve – Qstar, B
  • Amit Majumdar – Xilinx, USA
  • Erik Jan Marinissen – IMEC, B
  • Stephen Sunter – Mentor, USA
  • Baosheng Wang – AMD, USA

 

For more information, visit us on the web at: http://ttep.tttc-events.org/ttep/tutorials.html 

The Test Technology Educational Program 2016 is sponsored by the Institute of Electrical and Electronics Engineers (IEEE) Computer Society's Test Technology Technical Council (TTTC)


IEEE Computer Society- Test Technology Technical Council

TTTC CHAIR 
Chen-Huan CHIANG
Alcatel-Lucent - USA
E-mail chen-huan.chiang@alcatel-lucent.com

PAST CHAIR 
Michael NICOLAIDIS 
TIMA Laboratory - France 
Tel. +33-4-765-74696 
E-mail michael.nicolaidis@imag.fr

TTTC 1ST VICE CHAIR 
Matteo SONZA REORDA
Politecnico di Torino - ITALY
E-mail matteo.sonzareorda@polito.it

SECRETARY
Joan FIGUERAS
Un. Politec. de Catalunya - Spain
Tel. +34-93-401-6603
E-mail figueras@eel.upc.es

ITC GENERAL CHAIR 
Michael Purtell
Intersil 
- USA 
Tel. +1-408-372-6015 
E-mail m.purtell@ieee.org

TEST WEEK COORDINATOR
Yervant ZORIAN 
Synopsys, Inc.  USA 
Tel. +1-650-584-7120 
E-mail Yervant.Zorian@synopsys.com

TUTORIALS AND EDUCATION
Paolo BERNARDI
 
Politecnico di Torino
 - Italy
Tel. +39-011-564-7183
E-mail paolo.bernardi@polito.it

STANDARDS
Rohit KAPUR

Synopsys
, Inc. - USA
Tel. +1-650-934-1487
E-mail rkapur@synopsys.com

EUROPE
Giorgio DI NATALE
LIRMM - France
Tel. +33-467-41-85-01
E-mail giorgio.dinatale@lirmm.fr

MIDDLE EAST & AFRICA
Ibrahim HAJJ
American University of Beirut - Lebanon
Tel. +961-1-341-952
E-mail ihajj@aub.edu.lb

STANDING COMMITTEES 
André IVANOV 
University of British Columbia - Canada 
Tel. +1-604-822-6936 
E-mail ivanov@ece.ubc.ca

ELECTRONIC MEDIA 
Giorgio DI NATALE
LIRMM - France
Tel. +33-467-41-85-01
E-mail giorgio.dinatale@lirmm.fr

 

PRESIDENT OF BOARD 
Yervant ZORIAN
Synopsys, Inc.  USA 
Tel. +1-650-584-7120 
E-mail Yervant.Zorian@synopsys.com

SENIOR PAST CHAIR 
Adit D. SINGH  
Auburn University - USA  
Tel.  +1-334-844-1847  
E-mail adsingh@eng.auburn.edu

TTTC 2ND VICE CHAIR 
Rohit KAPUR
 
Synopsys, Inc. 
USA
Tel. +1-650-934-1487
E-mail rkapur@synopsys.com

FINANCE 
Chen-Huan CHIANG
Alcatel-Lucent - USA
E-mail chen-huan.chiang@alcatel-lucent.com

IEEE DESIGN & TEST EIC 
André IVANOV
U. of British Columbia Canada 
Tel. +1 
E-mail ivanov@ece.ubc.ca

TECHNICAL MEETINGS 
Chen-Huan CHIANG 
Alcatel-Lucent
 - USA
Tel. +1-973-386-6759
E-mail chenhuan@alcatel-lucent.com

TECHNICAL ACTIVITIES 
Matteo SONZA REORDA
Politecnico di Torino Italy
Tel.+39 090 7055
E-mail patrick.girard@lirmm.fr

ASIA & PACIFIC 
Kazumi HATAYAMA
Gumma University - Japan
Tel.+81-277-30-1111
E-mail k-hatayama@el.gunma-u.ac.jp

LATIN AMERICA 
Victor Hugo CHAMPAC
Instituto Nacional de Astrofisica - Mexico
Tel.+52-22-470-517
E-mail champac@inaoep.mx

NORTH AMERICA 
André IVANOV 
University of British Columbia - Canada 
Tel. +1-604-822-6936 
E-mail ivanov@ece.ubc.ca

COMMUNICATIONS
Cecilia METRA 
Università di Bologna - Italy
Tel. +39-051-209-3038 
E-mail cmetra@deis.unibo.it

INDUSTRY ADVISORY BOARD
Yervant ZORIAN
Synopsys, Inc.  USA 
Tel. +1-650-584-7120 
E-mail Yervant.Zorian@synopsys.com